1. Field of the Invention
This invention relates generally to the processing of data signals in communication systems and, more particularly, the processing of data signals in equalizer filter circuits. Equalizer filter circuits or adaptive filter circuits are used to compensate for distortion introduced into the channel during the transmission of the data signals. The present invention has particular applicability to modem units.
2. Description of the Prior Art
Referring to FIG. 1, a block diagram of a modem unit 10, according to the prior art, is shown. INPUT data signals, typically transmitted over a cable, are applied to A/D converter unit 11 of the modem unit 10. The output signal of A/D converter unit 11 is applied to demodulation unit 12. The demodulation unit 12 can generate a real signal portion R and an imaginary signal portion I. The signals R and I are applied to equalizer unit 13. The modified real and imaginary signals Rxe2x80x2 and Ixe2x80x2, resulting from processing within the equalizer unit, are applied to decision unit 14. The decision unit 14 provides the OUTPUT signals of modem unit 10 and generates an complex ERROR signal e which is applied to equalizer unit 13.
Referring to FIG. 2A, a block diagram of an equalizer unit 13, such as would be used in the modem unit 10 of FIG. 1 for processing a complex INPUT data signals X, is shown. The equalizer unit 13 includes a multiplicity N of stages. Each stage n of the equalizer unit 13 includes a delay line Dn. The delay lines D0xe2x88x92DNxe2x88x921 of all of the stages are coupled in series. The output terminal of each delay line Dn is coupled, in addition to the next sequential delay line Dn+1, to a multiplier unit Mn and to an input terminal of update unit Un. Each multiplier unit Mn also receives a coefficient signal Cn. The coefficient signal is a signal group stored in the update unit Un which is updated in update unit Un in response to an ERROR signal. An ERROR signal e is generated as a result the processing of each signal group in the decision unit 14 (as shown in FIG. 1). The product of the signals Cn and the output signal from delay line Dn formed in multiplier unit Mn is applied to adder unit An. The adder unit An receives an output signal from the previous sequential adder unit Anxe2x88x921 and the summation of the output signal for multiplier unit Mn and the output signal from adder unit Anxe2x88x921 is applied to the next sequential adder unit An+1. For a series of N delay lines, the input signal X is applied to delay line D0 and the output signal Xxe2x80x2 is applied to the output terminal of adder unit ANxe2x88x921. The delay line D0, shown with dotted lines, is not necessary for the operation of the typical filter, but this element is present in the implementation of the present invention.
The equalizer unit 13 shown in FIG. 2A is generally referred to as a direct form of an equalizer filter unit or adaptive filter unit. In FIG. 2B, the direct form of an equalizer unit is shown in which the series of adder units A1 through ANxe2x88x921 of FIG. 2A is replaced by an inverted adder tree in order to reduce latency required to perform the addition operation. Adder units A0 through AN/2 each receive signals from two multiplier units and apply output signals therefrom to adder tree circuit 21. Two output signals from the adder tree circuit 21 are applied to an adder unit AZ, which in turn has the OUTPUT signal Xxe2x80x2 applied to an output terminal thereof. As in FIG. 1, the delay line D0, shown with dotted lines, is not necessary in the implementation of the equalizer filter unit as illustrated. However, this element is used in the present invention.
In FIG. 2C, a transpose form of an equalizer unit is shown in which each stage has a configuration differing from the direct form. Each stage of the transpose form of the equalizer unit includes two delay lines, an update unit, a multiplier unit, and an adder unit. In this configuration, DATA IN signals are applied to each multiplier unit Mn associated with equalizer unit stage n and to the first delay line D0 in a series of a adder unit An/delay lines Dn. The multiplier unit Mn also has a coefficient value stored in update unit Un applied thereto. The input signal is also applied to series of delay lines Dxe2x80x2n, each delay line being associated with one stage of the nth stage equalizer filter unit. The INPUT signal groups are transmitted through the series of delay lines Dxe2x80x2n, however, the signal groups are transferred in the reverse sequential order from the flow of processed signal groups through the equalizer stages. The update unit Un receives output signals from a delay line Dxe2x80x2n associated with stage n. The output signals from multiplier unit Mn are applied to an nth stage adder unit An. The adder unit An has an output signal from delay Dn applied thereto and the output signal from adder An is applied to the input terminal of the (n+1)th stage delay line Dn+1. The output signal from delay line Dn+1 is applied to the input terminal of the An+1 adder unit associated with the (n+1)th equalizer filter unit stage. An ERROR signal e is also applied to update unit Un. The output signal from adder ANxe2x88x921 is the output signal of the equalizer filter unit. The delay line D0, the delay line Dxe2x80x2nxe2x88x921 and the adder unit A0, shown by dotted lines, are not necessary for the normal implementation of an equalizer filter, but are needed in the implementation of the present invention.
The input data signal X has a real part R and an imaginary part I. For each input data signal group, Xi=Ri+jIi. When k is equal to the number of the latest data signal group to be entered in the equalizer (also referred to as an iteration), then as will be clear to those familiar with equalizer units:
Xxe2x80x2k=Rxe2x80x2+jIxe2x80x2=xcexa3(i=0xe2x88x92 greater than Nxe2x88x921)C*i,kXkxe2x88x921.
and
Ci,k+1=Ci,k+xcexce*kXkxe2x88x921
where all the quantities except xcexc can be complex, * denotes the complex conjugate of the number and ek is the error signal generated by the decision unit after Xxe2x80x2k has been generated by the equalizer unit. As this equation indicates, the multiplier coefficients are updated. This requirement for updating these coefficients provides further complexity in the implementation of the equalizer unit.
In a typical equalizer unit, the number of delay lines N can be large. Because each delay line Dn is coupled to a multiplier unit Mn and an adder unit An, the equalizer unit 13 can occupy approximately one half of the area of the silicon chip on which the modem unit 10 has been fabricated.
A need has therefore been felt for apparatus and an associated method to reduce the number of components required to implement a modem unit, and particularly, the equalizer unit portion of the modem unit, in an integrated circuit.
The aforementioned and other features are accomplished, according to the present invention, by providing an equalizer unit or adaptive filter unit in which the unit, having N components, is divided into M segments. Of the M segments, only one segment has apparatus for up-dating the coefficients of each equalizer component within the segment. The equalizer unit further includes apparatus for cyclically transferring the data and the coefficient signal groups from one segment to the next consecutive segment. In addition, reconfiguration apparatus couples the segments in such a manner that the data continues to be transferred through the segments of the equalizer unit in the sequence established during an initialization of equalizer unit operation. The equalizer unit therefore reduces the apparatus used in the updating of the coefficients by a factor of approximately 1/M. However, by periodically cycling the coefficients through the equalizer unit, all the coefficients of the equalizer unit will be updated, but the coefficients will be updated approximately 1/N times as often as in the equalizer unit with a coefficient update unit for every component.
These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.